Isolating devices that are fabricated on a semiconductor substrate is a significant aspect of modern semiconductor chip manufacturing. This is especially true in very-large-scale integration ("VLSI") and ultra-large-scale integration ("ULSI") semiconductor chips because hundreds of thousands of devices are fabricated in a single semiconductor chip. If two transistors or other devices are fabricated too close to one another, they will not work because they will be electrically shorted together. In addition, incorrect isolation among transistors can cause current leakage and further escalate latch-up that can impair proper functioning of the circuits on the semiconductor chip either momentarily or permanently.
In metal-oxide-semiconductor ("MOS") transistor fabrication, isolation is accomplished by forming isolation regions between neighboring active regions on the semiconductor chip. These isolation regions are formed by ion-doping a channel stop of polarity opposite to the source electrode and the drain electrode of the integrated circuit device, and by growing a thick oxide, commonly referred to as a field oxide. The channel stop and the thick oxide cause the threshold voltage in the isolation region to be much higher than those of the neighboring active devices.
One common approach in the semiconductor industry for forming isolation regions is by the localized oxidation of silicon ("LOCOS") method. LOCOS uses a patterned silicon nitride ("Si.sub.3 N.sub.4 ") layer as an oxidation barrier mask and the silicon substrate is then selectively oxidized to form semi-planar isolation regions. The active devices are formed in the area defined by the silicon nitride layer. After oxidation, the silicon nitride layer is typically removed leaving a free area for the formation of the remaining circuit components.
An alternative to the LOCOS method of forming isolation regions is to use shallow trench isolation ("STI"). In this method, trenches are etched in the silicon substrate through microlithography techniques. The trenches are then filled using conventional deposition techniques with silicon dioxide, commonly some form of tetraethyl orthosilicate ("TEOS"). The silicon dioxide is then etched back or polished using chemical mechanical polishing ("CMP") to form the field oxide isolation regions.
As the active regions and the isolation regions in semiconductor devices have become more dense, it has been observed that a very small amount of transistors (approximately 5 out of 128,000) exhibit massive amounts of transistor leakage in some semiconductor chips. The transistor leakage experienced was not gate modulated so regular punch-through leakage was not the source of the transistor leakage. SEM micrographs of semiconductor chips that exhibit this transistor leakage have shown that the source and drain of the failed transistors were shorted by a punch-through killer defect in the channel of the failed transistors. While the source of this defect is not well understood, some references suggest that these defects may be stress related. Therefore, a need has arisen for a method of manufacturing a semiconductor chip that solves the problems associated with this defect in the channel of the failed transistors due to stress experienced during manufacturing.